1. Field of the Invention
The present invention relates to a reading method of a NAND-type memory device and to a NAND-type memory device.
2. Description of the Related Art
Minimizing the size of the devices is a major target to be achieved in the design of nonvolatile memories, as well as in almost all electronic applications. However, the reduction of the dimensions often involves problems that may not be disregarded, especially in some kinds of nonvolatile memories, such as NAND-type nonvolatile memory devices (NAND memories hereinafter).
A conventional NAND memory architecture will be described hereinafter, in order to focus on problems that increased and undesired capacitive coupling due to component miniaturization may cause.
As shown in FIG. 1, a NAND memory 1 comprises an array 2 of cells 3 arranged in rows and columns, an I/O buffer 4, a row decoder circuit 5, a column decoder circuit 6, a sensing stage 7, a regulated voltage generator 8 and a control unit 9. We will initially assume that cells 3 are single level flash memory cells, capable of storing one bit each. FIG. 2 shows the distribution of the threshold voltages corresponding to an erased state (1, negative threshold voltage VT) and to a programmed state (0, positive threshold voltage VT) for a cell 3. With reference to FIG. 3, cells 3 arranged on a same column are associated to a same bitline 10. More precisely, cells 3 of a same column are series connected in groups, normally of 16 or 32 elements, to form so-called strings or stacks, which are indicated by the reference number 12 in FIG. 3. First end terminals 12a of the stacks 12 are selectively connectable to a common ground line 13 through respective source selectors 15; and second end terminals 12b of the stacks 12 are selectively connectable to the respective bitline 10 through respective drain selectors 16. In the embodiment herein described, source selectors 15 and drain selectors 16 are NMOS transistors. Of course, stacks 12, source selectors 15 and drain selectors 16 are arranged in rows and columns. So, source selectors 15 arranged on a same row have their gate terminals connected to a same source select line 18 and drain selectors 16 arranged on a same row have their gate terminals connected to a same drain select line 19. Moreover, couples of adjacent bitlines 10 (one even and one odd) are connected to a respective page buffer circuit 20 in the sensing stage 7.
Gate terminals of cells 3 arranged on a same row are connected to a same wordline. In FIG. 3, wordlines are designated by symbols WL<M−1,N>, WL<M,N> where M designates a row of stacks 12 in the array 2 and N designates the position of a wordline in the respective row of stacks 12. In the example of FIG. 3, each stack 12 includes 32 cells 3, so N ranges from 0 to 31. So, in the M-th row of stacks 12, WL<M,0> designates the wordline coupled to the cells 3 having their source terminals directly connected to the respective source selectors 18, and WL<M,31> designates the wordline coupled to the cells 3 having their drain terminals directly connected to the respective drain selectors 19. There may be sixteen rows of stacks 12, for example.
NAND memory reading is usually based on charge integration and exploits the parasitic capacitance CP associated to each bitline 10 (illustrated by parasitic capacitors 21 in FIG. 3). When a cell 3 is selected for reading, the page buffer circuit 20 supplies an precharge current IPC to the corresponding bitline 10, until the parasitic capacitors 21 is charged to a predetermined drain read voltage VDR (e.g., 1.2 V to 1.4 V). Moreover, a gate read voltage VGR is provided on the wordline WL<M,N> coupled to the gate terminal of the selected cell 3, whereas wordlines coupled to the other cells 3 in the same stack 12 are set to a pass voltage VP. The gate read voltage VGR has such a value that the corresponding selected cell 3 may draw a current only in the erased state, but not in the programmed state. In other words, the gate read voltage VGR is intermediate between admissible threshold voltage levels corresponding to the erased state and to the programmed state. In the example of FIG. 2, VGR is 0 V. The pass voltage VP is as high as to turn on the corresponding cells 3 independently of their state (e.g., VP=5.5 V). Hence, all of the cells 3 which receive the pass voltage VP via the respective wordlines WL<M,N> are operated as pass gates.
During the step of charging the bitline 10, current is prevented from flowing through the selected stack 12 (i.e., the stack 12 including the selected cell 3) by turning off the respective source selector 15. To this end, a source control voltage VSS on the source select line 18 is set to 0 V. Instead, a drain control voltage VDS on the drain select line 19 is set to an appropriate voltage, so as to keep the drain selector 16 on (e.g., VDS=5.5 V).
When the bitline 10 has been charged to the drain read voltage VDR, the source selector 15 is turned on by raising the source control voltage VSS to an appropriate level (e.g., 4.5 V). Thus, the charge stored on the parasitic capacitor 21 associated to the selected bitline 10 is sunk by the selected cell 3, provided that the selected cell 3 is in the erased state. In this case, the voltage on the selected bitline 10 drops to substantially 0 V. If, on the contrary, the selected cell 3 is in the programmed state, no currents may flow and the voltage on the selected bitline 10 remains substantially unchanged. The page buffer circuit 20 then senses the voltage level on the selected bitline and provides output data, which is sent to the I/O buffer 4 through the column decoder circuit 6.
Problems may arise when a cell 3 is selected for reading, which is coupled to the wordline WL<M−1,0>, WL<M,0>, i.e., the closest wordline to the source select line 18 in the respective row of stacks 12. In fact, capacitive coupling is established between adjacent conductive lines, either wordlines WL<M,N>, source select lines 18 or drain select lines 19. Moreover, the closer the conductive lines are arranged, the stronger the capacitive coupling. By currently available semiconductor technologies, NAND memories may be made wherein conductive lines are spaced apart 100 nm only, i.e., approximately equal to the width of the conductive lines themselves. Thus, when the source control voltage VSS on the source select line 18 is raised after charging the selected bitline 10, the capacitive coupling produces a voltage swing on the adjacent wordline WL<M,0>, as shown in FIG. 4. The voltage swing may temporarily turn on the selected cell 3, even if the latter is in the programmed state. Therefore, the selected bitline 10 is discharged independently of the state of the selected cell 3 and a reading error occurs. The above described drawback is becoming increasingly important as the size of the NAND memories is reduced, and affects multilevel even more seriously. In multilevel memories, in fact, threshold voltage levels associated to different programming states and the corresponding gate reading voltage are separated by narrower gaps, as compared to single level memories, as shown in FIG. 5. Thus, even a small voltage swing caused by raising the source control voltage VSS may cause the actual voltage on the wordline WL<M,0> to depart from a nominal gate reading voltage, corresponding to a threshold voltage level, to such an extent that the selected cell 3 is turned on irrespective of its programming state. Therefore, reading errors may occur.